Analog-to-digital converters (ADCs) based on sigma-delta modulation have been widely used in digital audio and high precision instrumentation systems. More recently, with the rising of continuous-time sigma-delta modulator being used in nanometer Complementary metal-oxide-semiconductor (CMOS) designs, the sigma-delta ADCs are commonly used in infrastructure wideband radio receivers. In general, sigma-delta ADCs has a loop filter which comprises (a series of) one or more operational amplifier (opamp) integrators, where each opamp integrator may have a resister at the input, an opamp, and a capacitor in a feedback path. An Nth order sigma-delta ADCs can have N stages of opamp integrators in the loop filter arranged to generate an output for a coarse analog-to-digital converter to generate a pulse train. The pulse train is then provided to a digital-to-analog converter in a feedback path back to the loop filter to as an input. If the coarse ADC produces a 1-Bit digital output pulse train, the digital output is typically provided to a digital filter and a decimator to produce a multi-bit digital output.
The efficiency of a continuous-time sigma-delta modulator is a function of the signal gain of the stages in the loop filter. In designing continuous time sigma-delta (CTSD) ADCs, one of the design goals is to reduce integrator output swing for a given integrator gain, so that the amplifier distortion is smaller and the current consumption is lower. Topologies with beneficial characteristics such as desirable signal transfer functions (STF) are typically afflicted with low signal gain in the front-end stages, thereby limiting their efficiency. The low signal gain is a result of large swing at the integrator outputs which must be scaled to fit within the swing limitations of the employed circuitry. If the signal swing can be reduced without affecting the signal transfer function (STF), then the loop filter maintains the desirable properties while increasing efficiency. The integrator output swing is determined by coefficients' scaling and supply voltage headroom. When the integrator is scaled for smaller swing, the integrator's AC gain is also reduced. Such an implementation may result in large noise contribution from the following stages of opamp integrators. If the unscaled output swing of an integrator stage can be reduced, its signal gain after scaling will be increased. Thus, it is desirable to reduce opamp output swing without significantly affecting the STF and/or compromising noise performance.